Cache testability circuit for embedded diagnostics

Details Cache testability circuit for embedded diagnostics Cache testability circuit for embedded diagnostics

1993-07-06

1996-03-05

Beausoliel, Jr., Robert W.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365201, G06F 1100

Patent

active

054974585

ABSTRACT:
A memory write disable circuit which disables write operations to main memory during cache diagnostics and thus provides a generic means for testing cache memory systems. Disabling write operations to main memory allows the diagnostics to easily distinguish between cache hits and cache misses during diagnostics. The disable circuit operates by disabling the output enable for the main memory write signal. This disables writes to main memory in a manner external to the memory controller and thus allows tags to be loaded from a cacheable space in main memory. This enables the testing of cache memory systems in computer systems using integrated cache and memory controllers which prevent read hits to memory addresses whose cacheability has been disabled. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.

REFERENCES:
patent: 4575792 (1986-03-01), Keeley
patent: 5195096 (1993-03-01), Moore
patent: 5276833 (1994-01-01), Auvinen et al.
patent: 5287481 (1994-02-01), Lin
patent: 5341494 (1994-08-01), Thayer et al.

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