Cache tag parity detect circuit

Details Cache tag parity detect circuit Cache tag parity detect circuit

1991-03-29

1994-08-16

Beausoliel, Jr., Robert W.

Excavating

371 492, G06F 1110

Patent

active

053393228

ABSTRACT:
A memory which is cleared by simultaneously clearing a special bit in each entry within the memory, an extra bit, used for other purposes, is also cleared. When both bits have a value of 0, parity checking is disabled. When either bit has a value of 1, parity checking is enabled. This prevents incorrect detection of parity errors after the memory device has been cleared.

REFERENCES:
patent: 4084236 (1978-04-01), Chelberg et al.
patent: 4528666 (1985-07-01), Cline et al.
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4833601 (1989-05-01), Barlow et al.
patent: 4977498 (1990-12-01), Rastegar et al.
patent: 5056002 (1991-10-01), Watanabe
Cache memory systems benefit from on-chip solutions, vol. 32 No. 25, Dec. 10 1987 end electrical design news. p. 248, right col. line 1, p. 249, left column, line 5; figures 2, 4.

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