Cache tag memory

Static information storage and retrieval – Associative memories – Ferroelectric cell

Patent

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Details

365190, 365202, 36518907, 395445, 395280, 364253, G11C 1500, G11C 1300

Patent

active

054714150

ABSTRACT:
A comparator system for a cache tag RAM memory that makes use of data bus lines already available on the cache tag RAM. The true data bus lines are connected together at a connection point and form a "wired" connection or configuration. A "wired" connection may be for example, a "wired OR" "wired NOR" "wired AND" or "wired NAND" according to the present invention. The complement data bus lines on the cache tag RAM are connected in a similar fashion. The comparator system is connected to the cache tag RAM data bus lines and generates a hit or miss signal based on the data on the cache tag RAM data bus lines and input data that controls transistors connected to the cache tag RAM data bus lines, resulting in a faster comparison function.

REFERENCES:
patent: 5014240 (1991-05-01), Suzuki
patent: 5018099 (1991-05-01), Burrows
patent: 5034636 (1991-07-01), Reis et al.
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5226009 (1993-07-01), Arimoto

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