Cache system with access mode determination for prioritizing acc

Details Cache system with access mode determination for prioritizing acc Cache system with access mode determination for prioritizing acc

1996-07-25

1997-06-10

Swann, Tod R.

Boots, shoes, and leggings

395446, 395450, 364DIG1, G06F11316

Patent

active

056385374

ABSTRACT:
A cache memory operates in a first mode, in which a cache hit occurs, and in a second mode, in which a cache miss occurs. A data processor operates in a first state in which instructions are accessed from memory and in a second state in which data is accessed from memory. Cache memory has a condition setting circuit which distinguishes instruction caching from a data caching. The processor sends an access-type signal which is compared with the access-type set in the condition setting circuit. When the access-type signal does not coincide with the contents of the condition setting circuit, a third state is declared which links the main memory and cache memory.

REFERENCES:
patent: 4502110 (1985-02-01), Saito
patent: 4646237 (1987-02-01), Allen
patent: 4831581 (1989-05-01), Rubinfeld
patent: 4897783 (1990-01-01), Nay
patent: 4989140 (1991-01-01), Nishimukai et al.
M33245 (M32/CCM) "Nikkei Data Pro. Micro Processor", Sep., 1990, MC6-364-381.

Affiliated with

Also associated with

Rating

Cache system with access mode determination for prioritizing acc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache system with access mode determination for prioritizing acc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache system with access mode determination for prioritizing acc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-772579