Cache system for reducing memory latency times

Details Cache system for reducing memory latency times Cache system for reducing memory latency times

1992-09-16

1995-04-04

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 36424341, G06F 1212

Patent

active

054044847

ABSTRACT:
The improved cache system reduces the effects of latency times by utilizing a preload instruction inserted by the compiler into the code. The preload instruction is sent sufficiently in advance of the corresponding load instruction to guarantee that the relevant data is in the cache memory when the load instruction is received. In addition, the invention prevents the pollution of the cache with data that will only be used once during the expected lifetime of the data in the cache. This second feature of the invention assures that a large number of references to data that will only be used once does not result in the contents of the cache being replaced with the subsequent need to reload the contents after the data references have been completed.

REFERENCES:
patent: 4761731 (1988-08-01), Webb
patent: 5233702 (1993-08-01), Emma et al.
patent: 5239644 (1993-08-01), Seki et al.

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