Cache system and control method therefor

Details Cache system and control method therefor Cache system and control method therefor

1991-07-22

1993-02-09

Fleming, Michael R.

Boots, shoes, and leggings

364DIG1, 3642405, 36424341, 3642384, G06F 1316

Patent

active

051858797

ABSTRACT:
A cache system which, when a cache is a bus master, puts a CPU in a standby state and makes effective a signal common to the CPU and cache and a signal decided only by the cache, or when the CPU is the bus master, makes effective the signal common to the CPU and cache and the signal decided only by the CPU, or when at a cache miss, the cache gives the CPU a control signal requesting reexecution of memory access and a control signal to allow the memory system to accept memory access to thereby operate the cache dependently on the CPU, so that even when either the CPU or the cache is the bus master, signal transmit-receive with respect to the memory system is adapted to be carried out substantially at the same timing. Furthermore, where a cache miss occurs when the CPU accesses to single data, and in order to cope with the case that a plurality of data from the memory system to the cache are transferred, the data of address next to the accessed address by the CPU is initially transferred from the memory system to the CPU, thereafter data is transferred to the CPU while changing the address in a so-called round robin method, and at last the object data for the CPU is controlled to be transferred in parallel to the CPU and cache, thereby minimizing the number of times for data transfer from the memory system to the cache.

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patent: 4646233 (1987-02-01), Weatherford et al.
patent: 4661905 (1987-04-01), Bomba et al.

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