Cache system

Boots – shoes – and leggings

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Details

3642448, 3642434, 364DIG1, G06F 1314

Patent

active

052768538

ABSTRACT:
A cache system having a plurality of read-in ports through which data fetched from a main memory system can be transferred regardless of the type of the data fetch request. Further, each data fetch request is output from an available read-in port, during the data fetch operation for a previous data fetch request of the same type.

REFERENCES:
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patent: 4439829 (1984-03-01), Tsiang
patent: 4493033 (1985-01-01), Ziegler
patent: 4551799 (1985-11-01), Ryan et al.
patent: 4695943 (1987-09-01), Keeley
patent: 4707784 (1987-11-01), Ryan et al.
patent: 4755930 (1988-07-01), Wilson et al.
patent: 4835678 (1989-05-01), Kofuji
patent: 4914576 (1990-04-01), Zelley
Per Knudsen, "Supermini goes multiprocessor route to put it up front in performance", 8032 Electronics International, vol. 55 (1982) Aug. No. 16, New York, USA, pp. 112-117.

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