Cache subsystem for microprocessor based computer system with sy

Details Cache subsystem for microprocessor based computer system with sy Cache subsystem for microprocessor based computer system with sy

1991-06-04

1994-03-08

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642434, G06F 1208

Patent

active

052936031

ABSTRACT:
An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

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