Cache sub-array method and apparatus for use in microprocessor i

Details Cache sub-array method and apparatus for use in microprocessor i Cache sub-array method and apparatus for use in microprocessor i

1996-10-31

1998-09-22

Trans, Vincent N.

Boots, shoes, and leggings

711 3, G06F 1750

Patent

active

058124187

ABSTRACT:
A cache sub-array method and apparatus for use in microprocessor integrated circuits. A processor unit is disposed within a central region of the microprocessor integrated circuit; a peripheral region is designated as a cache memory array region and surrounds the central region; a predetermined number of cache memory sub-arrays are placed in the peripheral region such that variable size cache memory arrays may be efficiently created. The cache memory sub-arrays contain a fixed fraction of a total cache word. The microprocessor integrated circuit itself has a modular cache memory array of variable size, and includes a central region having a processor unit disposed therein, a peripheral region designated as a cache memory array region surrounding the central region, and a predetermined number of cache memory sub-arrays disposed in the peripheral region such that the cache memory sub-arrays compose a modular cache memory array of variable size.

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