Cache snoop latency prevention apparatus

Details Cache snoop latency prevention apparatus Cache snoop latency prevention apparatus

1993-12-16

1995-08-29

Robertson, David L.

G06F 1212

Patent

active

054468639

ABSTRACT:
A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

REFERENCES:
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
Practical Cache Design Techniques for Today's RISC and CISC CPUS, Jim Handy, Electro Conference Record, vol. 16, Apr. 16, 1991, pp. 283-288.
Futurebus+ Cache Coherence Jay Cantrell, Ire Wescon Convention Record, vol. 34, Nov., 1990, pp. 90-94.

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