Cache sharing control in a multiprocessor

Details Cache sharing control in a multiprocessor Cache sharing control in a multiprocessor

1981-12-30

1984-11-20

Thomas, James D.

Boots, shoes, and leggings

G06F 1516, G06F 900, G06F 1300

Patent

active

044842678

ABSTRACT:
The hybrid cache control provides a sharing (SH) flag with each line representation in each private CP cache directory in a multiprocessor (MP) to uniquely indicate for each line in the associated cache whether it is to be handled as a store-in-cache (SIC) line when its SH flag is in non-sharing state, and as a store-through (ST) cache line when its SH flag is in sharing state. At any time the hybrid cache can have some lines operating as ST lines, and other lines as SIC lines.
A newly fetched line (resulting from a cache miss) has its SH flag set to non-sharing (SIC) state in its location determined by cache replacement selection circuits, unless the SH flag for the requested line is dynamically set to sharing (ST) state and if a cross-interrogation (XI) hit in another cache is found by cross-interrogation (XI) controls, which XIs all other cache directories in the MP for every store or fetch cache miss and for every store cache hit of a ST line (having SH= 1).
A XI hit signals that a conflicting copy of the line has been found in another cache. If the conflicting cache line is changed from its corresponding MS line, the cache line is castout to MS. The sharing (SH) flag for the conflicting line is set to sharing state for a fetch miss, but the conflicting line is invalidated for a store miss.

REFERENCES:
patent: 4142234 (1979-02-01), Bean et al.
patent: 4394731 (1983-07-01), Flusche et al.
patent: 4399506 (1983-08-01), Evans et al.
patent: 4400770 (1983-08-01), Chan et al.
patent: 4410944 (1983-10-01), Kronies
patent: 4410946 (1983-10-01), Spencer

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