Cache resiliency in processing a variety of address faults

Details Cache resiliency in processing a variety of address faults Cache resiliency in processing a variety of address faults

1987-05-28

1989-05-23

Shaw, Gareth D.

Boots, shoes, and leggings

371 13, 371 51, 36424341, 3642653, G06F 1300, G11C 700

Patent

active

048336017

ABSTRACT:
A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

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