Patent
1994-12-21
1997-06-24
Robertson, David L.
395468, 395481, G06F 1200
Patent
active
056424949
ABSTRACT:
A cache memory with reduced request-blocking blocks requests from being accepted by the cache memory based on the types of requests the cache is already servicing. A request which hits the cache memory or a request which misses the cache memory but does not conflict with any requests already being serviced is not blocked. A request which misses the cache memory and also conflicts with a request(s) already being serviced causes the request to be blocked. In one embodiment, conflicts for write requests are determined by checking whether the cache is already retrieving a cache line from system memory for a request which maps into the same cache set as the write request. If such a request exists, then a conflict occurs. In this embodiment, conflicts for read requests are determined by checking whether the cache is already servicing an outstanding request to memory for the same address. If so, then a conflict occurs. If not, then a conflict does not occur unless the victim line for the read request is dirty and no space exists in a write-back buffer to temporarily store the victim line.
REFERENCES:
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 5434993 (1995-07-01), Liencres et al.
Val Popescu, et al., "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. 10-13 and 63-73.
Bauer John M.
Wang Wen-Hann
Intel Corporation
Robertson David L.
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