Cache memory with plurality of congruence sets and sense amplifi

Details Cache memory with plurality of congruence sets and sense amplifi Cache memory with plurality of congruence sets and sense amplifi

1993-08-03

1996-05-28

Swann, Tod R.

Boots, shoes, and leggings

395445, 364DIG1, G06F 1200

Patent

active

055220568

ABSTRACT:
A cache memory with a data memory divided into a plurality of word arrays, each of which is selectable by a word select indicator. Each word array is further divided into a plurality of bit arrays, each of which correspond to a bit of a word, and include congruence set memories for each congruence set. A bit array is connected to a sense amplifier via a congruence set selector, thereby one set of congruence set memories of the word arrays in the data memory is selected, and one congruence set memory is selected from each of the bit arrays by a congruence set selector to be connected with a sense amplifier, so that only one sense amplifier has to be provided for each bit in each word in an entry of the data memory, thus eliminating the need to increase the number sense amplifiers as the number of congruence sets increases. Furthermore, as only the sense amplifier associated with the selected word array is operational, current consumption is reduced.

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L. Liu "XOR Randomization in Cache Congruence Class Indexing" IBM Technical Disclosure Bulletin, vol. 27, No. 2 (Jul. 1984), p. 1097.
Interface, No. 123, Aug. 1987, CQ Publication.

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