Cache memory with a write buffer indicating way selection

Details Cache memory with a write buffer indicating way selection Cache memory with a write buffer indicating way selection

1993-09-22

1996-10-08

Robertson, David L.

395467, 395483, 395486, G06F 1300

Patent

active

055640346

ABSTRACT:
The present invention discloses a 2-way set-associative cache memory incorporating thereinto a write buffer. Tag entries corresponding to data entries within each bank are added valid bits and write reserve bits. The write reserve bit is set when a write request occurs and is reset when the requested write operation is completed. When a cache miss occurs, a replacement controller selects one of two data entries as a candidate for replacement (i.e., a data entry to which a corresponding write reserve bit is not set).

REFERENCES:
patent: 5155824 (1992-10-01), Edenfield et al.
Mike Johnson, "Superscalar Microprocssor Design", pp. 150-152 (1991).

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