Patent
1995-02-22
1996-12-31
Chan, Eddie P.
395440, 395445, 395403, G06F 1208
Patent
active
055903002
ABSTRACT:
A method for operating a cache memory system has a high speed cache memory and a mass storage device operates in a highly efficient manner with a host device. The method operates to dynamically assign segments of the cache memory to correspond to segments of the mass storage device, accept data written by the host into portions of the assigned segments of the cache memory, determines if the elapsed time since any modified data has been written to the cache memory exceeds a predetermined period of time, or if the number of modified segments exceeds a preset limit. If so, the cache memory system enables a transfer mechanism to cause modified data to be written from the cache memory to the mass storage device, based on the location of segments relative to a currently selected track of the mass storage device. Movement of updated data from the cache memory (solid state storage) to the mass storage device (which may be, for example, a magnetic disk) and of prefetched data from the mass storage to the cache memory is done on a timely, but unobtrusive, basis as a background task. A direct, private channel between the cache memory and the mass storage prevents communications between these two media from conflicting with transmission of data between the host and the cache memory system. A set of microprocessors manages and oversees the data transmission and storage. Data integrity is maintained in the event a power interruption via a battery assisted, automatic and intelligent shutdown procedure.
REFERENCES:
patent: 4086629 (1978-04-01), Desyllas et al.
patent: 4394733 (1983-07-01), Swenson
patent: 4433374 (1984-02-01), Hanson et al.
patent: 4433394 (1984-02-01), Hanson et al.
patent: 4437155 (1984-03-01), Sawyer et al.
patent: 4458307 (1984-07-01), McAnlis
patent: 4468730 (1984-08-01), Dodd
patent: 4490782 (1984-12-01), Dixon
patent: 4523206 (1985-06-01), Sasscer
patent: 4530054 (1985-07-01), Hamstra
patent: 4583166 (1986-04-01), Hartung
patent: 4603380 (1986-07-01), Easton et al.
patent: 4607346 (1986-08-01), Hill
patent: 4611289 (1986-09-01), Coppola
patent: 4636946 (1987-01-01), Hartung et al.
patent: 4835686 (1989-05-01), Furuya
patent: 4843542 (1989-06-01), Dashiell
patent: 4882642 (1989-11-01), Tayler et al.
patent: 4888691 (1989-12-01), George et al.
patent: 4908793 (1990-03-01), Yamagata
patent: 4920478 (1990-04-01), Furuya et al.
patent: 4956803 (1990-09-01), Tayler et al.
patent: 4959774 (1990-09-01), Davis
patent: 4972364 (1990-11-01), Barrett et al.
patent: 5043885 (1991-08-01), Robinson
patent: 5133060 (1992-07-01), Weber et al.
patent: 5159677 (1992-10-01), Rubsam et al.
patent: 5224217 (1993-06-01), Zangenehpour
patent: 5309451 (1994-05-01), Noya et al.
patent: 5325509 (1994-06-01), Lautzenheiser
patent: 5353430 (1994-10-01), Lautzenheiser
patent: 5410653 (1995-04-01), Macon, Jr. et al.
CMG '86 Las Vegas Dec. 9-12, 1986--Degradation of IMS Performance Using a 3880-23 Cache Controller by Carolyn Hanna, pp. 15-21.
CMG '86 Las Vegas Dec. 9-12 '86--Performance & Tuning of Cached I/O Subsystems by Mark B. Friedman, pp. 717-727.
CMG XV International Conf. of San Francisco Dec. 1984--Method for the Depoyment of IBM 3880 Model 13 Cached Storage Controllers by P. T. Guttman.
CMG Transactions Fifty-four, Fall 1986--Disc Caching in the System Processing Units of the JP 3000 Family of Computers by John R. Busch et al.
Research Report; RC 10197(#45223) Sep. 21, 1983 Computer Science--The Access Time Myth, by R. A. Scranton & D. A. Thompson, pp. 1-8.
IBM Systems Journal vol. 24, Nos. 3/4 1985 "Cache-DASD Storage Design for Improving System Performance", by Grossman, pp. 316-334.
International Business Machines Corp.--"A Multiple Workload Approach to Cache Planning" by B. McNutt & J. Murray, pp. 9-15.
CMG '87--The Computer Measurement Group, Inc. Orlando Dec. 7-11, 1987--BEST/1 Analysis of the IBM 3380-13 Cached Storage Controller by J. Buzen & Anneliese Von Mayrhauser, pp. 156-173.
Computer Science Division, University of California, Berkeley, "Maximizing Performance in Striped Disk Array" by P. Chen & D. Patterson, pp. 322-331, 1990.
University of California, Berkeley, Cache Memory Design: An Evolving Art, by A. J. Smith, pp. 40-44, 1987.
University of Wisconsin, "A Case for Direct-Mapped Caches" by M. D. Hill, Dec. 1988, pp. 25-40.
IBM, Almaden Research Center and Tucson Lab., "The IBM 3990 Disk Cache" by Jai Menon and Mike Hartung, pp. 146-151, 1988.
The Computer Society of IEEE, Feb. 29-Mar. 4, 1988 "COMPCON88", Nippon Electric Co., Tokyo, Japan, Integrated Disk Cache System with File Adaptive Control by Tokunaga et al., pp. 412-416.
1988 IEEE, Amperif Corp., "The Amperif Cache Disk System", by S. Fuld, pp. 156-157.
COMPCON88, Feb. 29-Mar. 4, 1988, Boole & Babbage, Inc. "DASD Cache Controllers: Performance Expectations and Measurements" by Kovach, pp. 74-78.
Caserza Steven F.
Chan Eddie P.
Nguyen Hiep T.
Zitel Corporation
LandOfFree
Cache memory utilizing address translation table does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache memory utilizing address translation table, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory utilizing address translation table will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1149268