Cache memory utilizing a two-phase synchronization signal for co

Details Cache memory utilizing a two-phase synchronization signal for co Cache memory utilizing a two-phase synchronization signal for co

1990-04-12

1994-03-15

Lee, Thomas C.

Boots, shoes, and leggings

395400, 364964, 3649642, 36496425, 36496434, 3649648, 364971, 364DIG2, G06F 1212

Patent

active

052952533

ABSTRACT:
A device for fast memory access in a computer system that employs a high-speed associative memory for storing extracts that each include an address and an associated information element. Each extract is associated with a presence flip-flop and a reference flip-flop, their respective states being changed when an extract is used. The device according to the invention is designed to operate using two clock phases. During a first clock phase, the device compares an address to be translated with each address contained in the high-speed associative memory, evaluates a saturation condition, and latches the result of this evaluation. During the second clock phase, the device updates reference indicators as a function of the coincidence signals which are latched during the first phase and of the latched evaluation signal. The invention can be used in conjunction with cache memories and for translation of virtual addresses to real addresses.

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