Cache memory system with improved re-writing address determinati

Details Cache memory system with improved re-writing address determinati Cache memory system with improved re-writing address determinati

1988-02-09

1990-02-27

Anderson, Lawrence E.

Boots, shoes, and leggings

3642434, 36424612, G06F 1300, G06F 1212

Patent

active

049051393

ABSTRACT:
A cache memory system having an improved area addressing scheme for rewriting is disclosed. The cache memory system comprises a cache memory having a plurality of memory areas, a first detection circuit for designating the least recently accessed area by a CPU, a second detection circuit for detecting that the least recently accessed memory area is not designated and a control circuit for forcibly selecting a predetermined one memory area for rewriting when the least recently accessed memory area is not designated.

REFERENCES:
patent: 4442488 (1984-04-01), Hall

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