Cache memory system having multiple caches with each cache mappe

Details Cache memory system having multiple caches with each cache mappe Cache memory system having multiple caches with each cache mappe

1995-06-05

1998-04-07

Swann, Tod R.

395446, 395470, G06F 1210

Patent

active

057375640

ABSTRACT:
A cache memory system includes a plurality of processors and a plurality of caches respectively assigned to the plurality of processors. Each cache is mapped to a different region of the main memory, so that memory contention is lessened to a great extent. Based on a memory address received by a cache, the cache compares the memory address to its assigned region of addresses. If the memory address falls within the assigned region for the cache, the cache then examines its contents as to determine if there is an address hit in the cache. If the memory address does not fall within the assigned region for the cache, the cache does not examine its contents to determine if there is an address hit in the cache, since an address hit is not possible in that case.

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Computer Design, Warren Andrews, "New Cache Tags Bring Flexibility, Performance to Memory Subsystems", Jul. 1, 1990, pp. 42-46.
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IBM Technical Disclosure Bulletin, "Memory Management Mechanism To Reduce Cache-Line Contention", Anonymous, vol. 32, No. 8B, Jan. 1990, pp. 25-26.
Patent Abstracts of Japan, vol. 015, No. 122 (P-1184), Mar. 26, 1991, abstract of Ishida Itsuko et al., "Data Processor", Japanese 03 01-345, Jan. 17, 1991.

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