Cache memory system having a plurality of ports

Details Cache memory system having a plurality of ports Cache memory system having a plurality of ports

1993-12-21

1997-01-14

Chan, Eddie P.

Boots, shoes, and leggings

395458, 395464, 364DIG1, 36424342, G06F 1208

Patent

active

055948847

ABSTRACT:
An instruction cache and a data cache are formed with a 2-port structure, the first port of the instruction cache is exclusively used for readout of the contiguous instruction, and the second port thereof is exclusively used for readout of the branched instruction when the conditional branch instruction is executed. With this construction, two instructions which may be executed can be simultaneously fetched irrespective of whether the branch of the conditional branch instruction is taken or untaken, thereby making it possible to enhance the CPU performance. Further, in the 2-port data cache, time for the cache refill process can be reduced by means of the contiguous data transfer and non-cacheable access.

REFERENCES:
patent: 5177706 (1993-01-01), Shinohara et al.
patent: 5274790 (1993-12-01), Suzuki
patent: 5287465 (1994-02-01), Kurosawa
patent: 5287467 (1994-02-01), Blaner et al.
patent: 5313587 (1994-05-01), Patel et al.
patent: 5434989 (1995-07-01), Yamaguchi
patent: 5465344 (1995-11-01), Hirai et al.

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