Boots – shoes – and leggings
Patent
1993-12-22
1996-07-30
Lim, Krisna
Boots, shoes, and leggings
395417, 395445, 395449, 36424341, 36424345, B06F 1208
Patent
active
055420621
ABSTRACT:
A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.
REFERENCES:
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4464712 (1984-08-01), Fletcher
patent: 4612612 (1986-09-01), Woffinden et al.
patent: 4701844 (1987-10-01), Thompson et al.
patent: 4707784 (1987-11-01), Ryan et al.
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4736293 (1988-04-01), Patrick
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4774654 (1988-09-01), Pomerene et al.
patent: 4785395 (1988-11-01), Keeley
patent: 4797814 (1989-01-01), Brenza
patent: 4807110 (1989-02-01), Pomerene et al.
patent: 4823259 (1989-04-01), Aichelmann, Jr. et al.
patent: 4831622 (1989-05-01), Porter et al.
patent: 4926317 (1990-05-01), Wallach et al.
patent: 4980823 (1990-12-01), Liu
patent: 4985829 (1991-01-01), Thatte et al.
patent: 4991081 (1991-02-01), Bosshart
patent: 5018061 (1991-05-01), Kishigami et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5095424 (1992-03-01), Woffinden et al.
patent: 5136700 (1992-08-01), Thacker
patent: 5163140 (1992-11-01), Stiles et al.
patent: 5266133 (1993-07-01), Taylor et al.
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5307477 (1994-04-01), Taylor et al.
Baskett, et al., "The 4D-MP Graphics superworkstation: Computing+ Grphics= 40 MIPS+ 40 Mflops . . .," 33rd IEEE Computer Soc. Intl. Conf. (Spring, 1988), pp. 468-471.
Stone, High-performance Computer Architecture, Addison-Wesley, Reading, Mass., 1987, pp. 29-69.
Taylor, et al., "An ECL RISC Microprocessor Designed for Two Level Cache," 35th IEEE Computer Soc. Int. Conf. (Spring, 1990), pp. 228-231.
Farmwald P. Michael
Layman Timothy P.
Ngo Huy X.
Roberts Allen W.
Taylor George S.
Lim Krisna
Silicon Graphics Inc.
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