Patent
1995-08-04
1997-10-07
Gossage, Glenn
395417, 395403, G06F 1212, G06F 1300
Patent
active
056757638
ABSTRACT:
A cache memory system and method for selectively removing stale "aliased" entries, which arise when portions of several address spaces are mapped into a single region of real memory, from a virtually addressed cache, are described. The cache memory system includes a central processor unit (CPU) and a first-level cache on an integrated circuit chip. The CPU receives tag and data information from the first level cache via virtual address lines and data lines respectively. An off-chip second level cache is additionally coupled to provide data to the data lines. The CPU is coupled to a translation lookaside buffer (TLB) via the virtual address lines, while the second level cache is coupled to the TLB via physical address lines. The first and second level caches each comprise a plurality of entries. Each of the entries includes a status bit, indicating possible membership in a class of entries that might require flushing. Address translation database entries (page table entries or translation lookaside buffer (TLB) entries) are augmented with a field that contains the appropriate value of the status bits of each first and second level cache entry. Status bits are set for any page in which stale aliases may potentially occur (i.e., those shared pages that can be modified by at least one process or device). The cache-fill mechanism includes a path combining the status bits with the data being loaded into the first-level cache.
REFERENCES:
patent: 4525778 (1985-06-01), Cane
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4774659 (1988-09-01), Smith et al.
patent: 5003459 (1991-03-01), Ramanujan et al.
patent: 5119290 (1992-06-01), Loo et al.
patent: 5146603 (1992-09-01), Frost et al.
patent: 5214770 (1993-05-01), Ramanujan et al.
patent: 5278964 (1994-01-01), Mathews et al.
Digital Equipment Corporation
Fisher Arthur W.
Gossage Glenn
Hudgens Ronald C.
McGuinness Lindsay G.
LandOfFree
Cache memory system and method for selectively removing stale al does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache memory system and method for selectively removing stale al, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory system and method for selectively removing stale al will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2365163