Cache memory system

Details Cache memory system Cache memory system

1988-04-01

1991-03-26

Fleming, Michael R.

Boots, shoes, and leggings

36424341, 36424344, 3642563, G06F 1212

Patent

active

050034596

ABSTRACT:
The invention is directed to a cache memory system in a data processor including a virtual cache memory, a physical cache memory, a virtual to physical translation buffer, a physical to virtual backmap, an Old-PA pointer and a lockout register. The backmap implements invalidates by clearing the valid flags in virtual cache memory. The Old-PA pointer indicates the backmap entry to be invalidated after a reference misses in the virtual cache. The physical address for data written to virtual cache memory is entered to Old-PA pointer by the translation buffer. The lockout register arrests all references to data which may have synonyms in virtual cache memory. The backmap is also used to invalidate any synonyms.

REFERENCES:
patent: 4332010 (1982-05-01), Messina et al.
patent: 4513367 (1985-04-01), Chan et al.
patent: 4602368 (1986-07-01), Circello et al.
patent: 4654819 (1987-03-01), Stiffler et al.
patent: 4785398 (1988-11-01), Joyce et al.
patent: 4807110 (1989-02-01), Pomerene et al.
patent: 4811209 (1989-03-01), Rubinstein
patent: 4814981 (1989-03-01), Rubinfeld
patent: 4831520 (1989-05-01), Rubinfeld et al.
patent: 4831581 (1989-05-01), Rubinfeld
patent: 4851991 (1989-07-01), Rubinfeld et al.

Affiliated with

Also associated with

Rating

Cache memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-622058