Cache memory support in an integrated memory system

Details Cache memory support in an integrated memory system Cache memory support in an integrated memory system

1993-11-30

1995-09-26

Kriess, Kevin A.

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395162, 395164, 395135, 395148, 395133, 395161, 395650, 395492, 39549704, 364DIG1, G06F 1520, G06F 1300

Patent

active

054541077

ABSTRACT:
A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.

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Gwennap, Linley, "Alpha Hits Low End with Digital's 21066--First Microprocessor to Integrate PCI Bus Interface", Microprocessor Report, vol. 7, No. 12, pp. 1, 6-8 and 16, Sep. 13, 1993.
64200 (Wingine.TM.) High Performance "Windows.TM. Engine", Chips and Technologies, Inc. Revision 0.6, pp. 5-11 and 96-97, Jul. 1992.

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