Cache memory simultaneously updating for a miss and deciding on

Details Cache memory simultaneously updating for a miss and deciding on Cache memory simultaneously updating for a miss and deciding on

1990-06-18

1993-05-11

Fleming, Michael R.

Boots, shoes, and leggings

364DIG2, 3649483, 3649550, 3649551, 3649561, 3649579, 3649576, 3649583, 3649621, 3649642, 36496421, 36496424, 36496425, 36496434, 3649654, G06F 932, G06F 1200

Patent

active

052108490

ABSTRACT:
In a cache memory simultaneously conducting updating for a miss and a decision on a miss for the subsequent address, a write flag generated by a control unit is written in a valid flag field. Based on this operation, during an access to an external memory at an occurrence of a miss, a tag field and the valid flag field are simultaneously updated. When updating a data field, a read operation is achieved on the tag and valid flag fields to decide occurrence of miss. Thus, an external memory access for a miss at a next address can be executed at an earlier point of time. Moreover, by the provision of a data latch disposed for an output from the data field, and by reading data at a next address and keeping it in the data latch during a memory read cycle, succeeding hit data can be outputted immediately after a miss processing is completed. Furthermore, also in a cache memory having a plurality of tag fields and a plurality of valid flag fields, the updating for a miss and the decision on a miss for a next address can be attained at the same time.

REFERENCES:
patent: 4228503 (1980-10-01), Waite et al.
patent: 4768148 (1988-08-01), Keeley et al.
patent: 4851993 (1989-07-01), Chen et al.
patent: 4905141 (1990-02-01), Brenza
patent: 4928239 (1990-05-01), Baum et al.
patent: 4953073 (1990-08-01), Moussouris et al.
patent: 4954944 (1990-09-01), Ikeda
patent: 5014240 (1991-05-01), Suzuki et al.
patent: 5019971 (1991-05-01), Lefsky et al.
patent: 5032985 (1991-07-01), Curran et al.
patent: 5056002 (1991-10-01), Watanabe
patent: 5070444 (1991-12-01), Kubo et al.
patent: 5097409 (1992-03-01), Schwartz et al.
patent: 5097414 (1992-03-01), Tone
patent: 5109498 (1992-04-01), Kamiy et al.

Affiliated with

Also associated with

Rating

Cache memory simultaneously updating for a miss and deciding on does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache memory simultaneously updating for a miss and deciding on , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory simultaneously updating for a miss and deciding on will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1357574