Cache memory integrated circuit for use with a synchronous centr

Details Cache memory integrated circuit for use with a synchronous centr Cache memory integrated circuit for use with a synchronous centr

1991-06-04

1993-07-13

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642386, 36423951, 3642434, G06F 1208, G06F 1228

Patent

active

052281345

ABSTRACT:
An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

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