Cache memory including master and local word lines coupled to me

Details Cache memory including master and local word lines coupled to me Cache memory including master and local word lines coupled to me

1996-03-11

1997-06-17

Swann, Tod R.

Static information storage and retrieval

Interconnection arrangements

364DIG1, 364DIG2, 365 49, 365 51, 36523006, 395481, G11C 700, G11C 800, G06F 1300

Patent

active

056403399

ABSTRACT:
An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. A first plurality of memory cells coupled to the master word lines stores access information corresponding to a plurality of data words stored in a second plurality a memory cells coupled to a plurality of local word lines. The cache stores tag, index and Least Recently Used (LRU) information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The cache includes circuitry for efficiently updating the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.

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