Cache memory having self-error checking and sequential verificat

Details Cache memory having self-error checking and sequential verificat Cache memory having self-error checking and sequential verificat

1988-02-16

1990-01-02

Smith, Jerry

Excavating

371 23, G01R 1122

Patent

active

048918091

ABSTRACT:
A multilevel cache memory system has a pseudo-error indicating flag for storing a first logic state when the system is in a normal error checking mode and a second logic state when the system is in a pseudo-error verification mode. First logic gate circuits, associated respectively with the levels of the cache memory, are arranged to be disabled in response to the first logic state and enabled in response to the second logic state. Register stages corresponding in number to the levels of the cache memory stores level-invalidating data. Second logic gate circuits are associated respectively with the register stages for sequentially activating one of the first logic gate circuits in accordance with logic states of the register stages when the first logic gate circuits are enabled. Second flags are associated respectively with the first logic gate circuits to give an error indication in response to the activated first logic gate circuits.

REFERENCES:
patent: 4686621 (1987-08-01), Keeley et al.

Affiliated with

Also associated with

Rating

Cache memory having self-error checking and sequential verificat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache memory having self-error checking and sequential verificat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory having self-error checking and sequential verificat will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1388386