Cache memory having pseudo virtual addressing

Details Cache memory having pseudo virtual addressing Cache memory having pseudo virtual addressing

1989-03-07

1992-11-17

Shaw, Gareth D.

Boots, shoes, and leggings

395425, 364DIG1, 364DIG2, 3642434, 3642563, 3649612, G06F 1210

Patent

active

051650282

ABSTRACT:
Cache memory having pseudo virtual addressing, in which the addressing is performed by using the "offset" field of a current address and a physical address field of an address previously used and stored in a first register, and where, for each logical current address a comparison is made between the logical page addresses of the current address and that of the last used physical address which is stored in a second register. Along with the requested information the cache memory outputs, if available, the effective physical page address of the information, which is compared with the physical page address used for addressing and stored in the first register. In this way, the addressing is performed by physical addresses but without need to wait for translation of a virtual/logical address into a physical address.

REFERENCES:
patent: 4386402 (1983-05-01), Toy
patent: 4400774 (1983-08-01), Toy
patent: 4550368 (1985-10-01), Bechtolsheim
patent: 4737909 (1988-04-01), Harada
patent: 4803621 (1989-02-01), Kelly
patent: 4884197 (1989-11-01), Sachs et al.

Affiliated with

Also associated with

Rating

Cache memory having pseudo virtual addressing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache memory having pseudo virtual addressing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory having pseudo virtual addressing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1178310