Patent
1993-09-01
1996-09-24
Robertson, David L.
395445, G06F 1314
Patent
active
055599850
ABSTRACT:
A microprocessor incorporating a cache memory unit according to the present invention sets at the register the number of bus cycles activated by the bus cycle control circuit for replacement when a miss occurs at the cache memory, through the program executed at the instruction execution unit according to whether the accessed data are contiguous or non-contiguous. The number counted at the counter of the activated bus cycles and the number set and held at the register are compared by the comparer. The comparer outputs the replacement completion signal when they are identical. The cache control circuit outputs the replacement request signal to request bus cycle activation to the bus cycle control circuit until receipt of the replacement completion signal from the comparer.
REFERENCES:
patent: 4315312 (1982-02-01), Schmidt
NEC Corporation
Robertson David L.
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