Cache memory having a variable data block size

Details Cache memory having a variable data block size Cache memory having a variable data block size

1979-12-19

1982-02-09

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1300

Patent

active

043153127

ABSTRACT:
A cache memory has a data buffer for storing blocks of data from a main memory and an index for storing main memory addresses associated with the data blocks in the data buffer. The size of the blocks of data stored in the data buffer can be varied in order to increase the "hit ratio" of the cache memory. The index is a set associative memory and bits provided to an address input of the index are selectively inhibited by an address inhibit circuit when the size of the data blocks in the data buffer is to be varied. A block size register stores block size information that is provided to the address inhibit circuit. The block size information is also provided to a fetch generate counter and a fetch return counter that control the number of words transferred as a block from the main memory to the cache memory.

REFERENCES:
patent: 3764996 (1973-10-01), Ross
patent: 4047243 (1977-09-01), Dijkstra
patent: 4161024 (1979-07-01), Joyce
patent: 4219883 (1980-08-01), Kobayashi et al.
patent: 4234934 (1980-11-01), Thersrud
Computer Organization, Ivan Flores, Prentice-Hall Inc., Chapter 9, pp. 228-237, 1969.

Affiliated with

Also associated with

Rating

Cache memory having a variable data block size does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache memory having a variable data block size, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory having a variable data block size will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1263597