Cache memory for efficient access with address selectors

Details Cache memory for efficient access with address selectors Cache memory for efficient access with address selectors

1994-10-11

1995-07-18

Harvey, Jack B.

Boots, shoes, and leggings

395425, 364228D, 3642281, 36424291, 36424341, G06F 1200, G06F 1208, G06F 1300

Patent

active

054349893

ABSTRACT:
A cache memory device including first and second address selectors and a control device for controlling the selection of two addresses out of four types of addresses. The four address types are instructions addresses successively generated by an increment of a program counter, a branch address for instruction fetch in a branch target based on a conditional branch instruction or the like, a data address for data access based on load instruction or store instruction, and a physical address for regulating data consistency between the cache memory device and other memory devices. A first memory array for storing tag addresses and a second memory array for storing instructions and data have two ports to access two selected addresses received from the first and second address selectors independently. Accordingly, access penalties by an RISC microprocessor are reduced in a processor unit in a multiprocessor system.

REFERENCES:
patent: 5056002 (1991-10-01), Watanabe
patent: 5133058 (1992-07-01), Jensen
patent: 5195089 (1993-03-01), Sindhu et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5228135 (1993-07-01), Ikumi
patent: 5247649 (1993-09-01), Bandoh
J. Archibald et al., Cache Coherence Protocols: Evaluation Using A Multiprocessor Simulation Model, ACM Trans. On Computer Systems, vol. 4, No. 4, pp. 273-298 (Nov. 1986).

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