Cache memory expansion and transparent interconnection

Details Cache memory expansion and transparent interconnection Cache memory expansion and transparent interconnection

1992-05-07

1993-10-12

Eng, David Y.

Boots, shoes, and leggings

395250, 3642403, 3642434, 3649642, G06F 1300

Patent

active

052533581

ABSTRACT:
A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

REFERENCES:
patent: 4237543 (1980-12-01), Nishio
patent: 4271466 (1981-06-01), Yamamoto
patent: 4442487 (1984-04-01), Fletcher
patent: 4447878 (1984-05-01), Kinnie
patent: 4853846 (1989-08-01), Johnson et al.
S. Domen, Tech Bits: A 64-Kbyte Solution for the 82385, No. 82385-PFG, Intel Corp. (Jun. 16, 1988).
Intel Corp., 1 Microprocessor and Peripheral Handbook: Microprocessor 4-287 to 4-332 (1988).

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