Cache memory device including word line driver circuit and...

Details Cache memory device including word line driver circuit and... Cache memory device including word line driver circuit and...

2003-05-08

2004-05-18

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050, C365S189080

Reexamination Certificate

active

06738278

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to cache memories, and more particularly, to a cache memory device including a word line driver circuit and method capable of increasing operational speed and yielding a reduction in the chip area of a semiconductor integrated circuit.
2. Description of the Related Art
A typical computer system includes main memory, such as dynamic random access memory (“DRAM”), and cache memory. Each memory cell block in the cache memory has an inherent tag address, and each tag address is checked to determine whether it is the same as an address received from a central processing unit (“CPU”). Content addressable memory (“CAM”) is used in comparing each tag address with an address received from the CPU. In general, the case where a tag address is the same as an address input from a CPU is called a ‘hit’, and the reverse case is called a ‘miss’.
FIG. 1
is a schematic block diagram of a typical cache memory device
100
having CAM cells, and
FIG. 2
is a detailed circuit diagram of a typical CAM cell
200
. Referring to
FIG. 1
, a tag address for a memory cell block
101
is stored in CAMs CAM
11
through CAM
1
n, a tag address for a memory cell block
102
is stored in CAMs CAM
21
through CAM
2
n, and that for a memory cell block
103
is stored in CAMs CAMm
1
through CAMmn. Only one of the stored tag addresses will be the same as an address input from a CPU (not shown), so that a ‘hit’ occurs only once.
A dynamic node CHIT
1
is commonly connected to the CAMs CAM
11
through CAM
1
n, and a dynamic node CHIT
2
is commonly connected to the CAMs CAM
21
through CAM
2
n. Similarly, a dynamic node CHITm is commonly connected to CAMs CAMm
1
through CAMmn.
All of the dynamic nodes CHIT
1
through CHITm are initially precharged to a line voltage level. The precharged line voltage level of each dynamic node is maintained if an address input from the CPU is the same as the tag address stored in the related CAMs, i.e., if a ‘hit’ occurs. If this is not so, i.e., if a ‘miss’ occurs, each dynamic node discharges until reaching a ground voltage level.
For instance, when an n-bit address input from the CPU is the same as a tag address stored in the CAMs CAM
11
through CAM
1
n, the precharged line voltage level of only the dynamic node CHIT
1
is maintained and the other dynamic nodes CHIT
2
through CHITm discharge until reaching a ground voltage level.
As a result, only a word line driver circuit
104
connected to the dynamic node CHIT
1
is enabled, and only a word line WL
1
of the memory cell block
101
is activated. Word line driver circuits
105
and
106
connected to the other dynamic nodes CHIT
2
and CHITm are disabled, and the word lines WL
2
through WLm are inactivated.
A comparison of a tag address with an address input from a CPU using CAMs has a first problem in that it is difficult to know the exact point in time when the comparison has completed according to the structural features of a CAM. This first problem will now be described in detail with reference to the CAM cell
200
shown in FIG.
2
. First, an input of a precharge signal PCH having logic ‘0’ causes a precharge PMOS transistor P
1
to turn on and a dynamic node CHIT to be precharged to a line voltage level VDD. After a predetermined amount of time, the precharge signal PCH reaches logic ‘1’, which causes the precharge PMOS transistor P
1
to turn off and an NMOS transistor N
4
to turn on.
If one bit TA of a tag address stored in a CAM cell shown in
FIG. 2
is at logic ‘1’ and one bit CA of an address input from a CPU (not shown) is at logic ‘0’, i.e., a complementary bit TAB of the bit TA is at logic ‘0’ and a complementary bit CAB of the bit CA is at logic ‘1’, a transmission gate TM
2
is turned on, a transmission gate TM
1
is turned off, and a pull-down NMOS transistor N
3
is turned on. As a result, the dynamic node CHIT discharges until reaching a ground voltage level VSS.
Meanwhile, if the bit TA of a tag address stored in a CAM cell is at logic ‘1’ and the bit CA of the address input from the CPU is at logic ‘1’, i.e., a complementary bit TAB of the bit TA is at logic ‘0’ and a complementary bit CAB of the bit CA is at logic ‘0’, the transmission gate TM
2
is turned on, the transmission gate TM
1
is turned off, and a pull-down NMOS transistor N
3
is turned off. As a result, the precharged line voltage level of the dynamic node CHIT is maintained.
In other words, in the event that the bit TA of the tag address stored in the CAM cell is not the same as the bit CA of the address input from the CPU, i.e., a ‘miss’ occurs, the dynamic node CHIT discharges until reaching a ground voltage level VSS. However, if the bit TA of the tag address stored in the CAM cell is the same as the bit CA of the address input from the CPU, i.e., a ‘hit’ occurs, the precharged line voltage level VDD of the dynamic node CHIT is maintained.
In the latter case, i.e., when a ‘hit’ occurs, a second problem is that it is difficult to know the exact point in time when the comparison of a tag address and an address input from a CPU has completed since the precharged level of the dynamic node CHIT is maintained, i.e., an event due to transition does not occur.
Turning to
FIG. 3
, a conventional method of solving this second problem is described with respect to a typical cache memory device
300
. The device
300
uses a dummy CAM miss path that is made to be always mismatched. Thus, a path having dummy CAM cells
1
through n is commonly connected to a dummy dynamic node Dummy CHIT. The dummy dynamic node Dummy CHIT is commonly connected to word line drivers
304
through
306
.
The dummy CAM miss path models the CAM miss path for a worst case scenario so that a ‘miss hit’ always occurs in the dummy CAM miss path. The CAM miss path for a worst case scenario refers to a CAM miss path having the slowest discharging operation in which only one cell of the CAM cells, which are connected to the dynamic node Dummy CHIT, is discharged.
However, it is difficult to design the dummy CAM miss path completely based on the model of the CAM miss path for the worst case scenario by the conventional method of using the cache memory device of FIG.
3
. Even if the dummy miss path completely models the CAM miss path for the worst case during the design of a semiconductor integrated circuit, the timing of the dummy CAM miss path may be not the same as that of the CAM miss path for the worst case scenario, due to a variation in a process of fabricating a semiconductor integrated circuit or variation in temperature. This difference would lower the operational speed of the cache memory device of
FIG. 3
using the conventional method.
Also, the conventional method requires the inclusion of a dummy CAM miss path including dummy CAM cells
1
through n into a semiconductor integrated circuit
300
as shown in
FIG. 3
, thereby increasing the chip area of such a semiconductor integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides a cache memory device having a word line driver circuit that is capable of increasing the operational speed of the cache memory device and causing a reduction in the chip area of a semiconductor integrated circuit.
The present invention also provides a method of driving a word line of a cache memory device that increases the operational speed of the cache memory device and causes a reduction in the chip area of a semiconductor integrated circuit.
According to one aspect of the present invention, there is provided a cache memory device including a first memory cell block; a second memory cell block; a plurality of first content addressable memory (“CAM”) cells for storing a tag address of the first memory cell block and commonly connected to a first dynamic node; a plurality of second CAM cells for storing a tag address of the second memory cell block and commonly connected to a second dynamic node; and a first word line driver circuit for driving a word line of the first memory cell block in response to signals output from the firs

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