Patent
1995-09-18
1996-07-23
Bayerl, Raymond J.
395164, G06F 1206
Patent
active
055398740
ABSTRACT:
A cache memory device stores image data which are arranged corresponding to address data having first and second two-dimensional coordinate data. The image data are divided into a plurality of first groups in accordance with the first two-dimensional coordinate data, with the first groups further divided into a plurality of second groups in accordance with the second two-dimensional coordinate data. The cache memory device includes an image data memory for storing a given image data therein, which is divided into a plurality of block areas arranged in two dimensions. The reading and writing of image data from and to the image data memory is controlled by a central processing unit. A cache storage, comprising a cache memory, an address data decoding circuit, an address matching circuit and a control circuit, is coupled between the image data memory and the central processing unit by way of buses.
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Stone, Harold S., High Performance Computer Architecture, pp. 31-42 (Japanese article, and English translation).
Komoto Eiji
Maki Kazuhiko
Bayerl Raymond J.
Challhan U.
Manzo Edward D.
Murphy Mark J.
OKI Electric Industry Co., Ltd.
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