Cache memory device constituting a memory device used in a compu

Details Cache memory device constituting a memory device used in a compu Cache memory device constituting a memory device used in a compu

1988-03-25

1991-02-12

Heckler, Thomas M.

Boots, shoes, and leggings

36496422, 36496423, G06F 1208

Patent

active

049929771

ABSTRACT:
A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.

REFERENCES:
patent: 4445174 (1984-04-01), Fletcher
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4802085 (1989-01-01), Levy et al.
patent: 4807110 (1989-02-01), Pomerene et al.
Electronics International, vol. 55, No. 16, Aug. 1982, pp. 112-117, New York, U.S.: P. Knudsen: "Supermini Goes Multiprocessor Route To Put It Up Front In Performance".

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