Cache memory controllor associated with microprocessor

Details Cache memory controllor associated with microprocessor Cache memory controllor associated with microprocessor

1989-04-12

1991-05-07

Chan, Eddie P.

Boots, shoes, and leggings

36424341, 3642329, 364271, G06F 1328

Patent

active

050141880

ABSTRACT:
A cache memory controllor according to the present invention sequentially checks into a controlling circuit to see whether or not data words accessed are memorized in a cache memory and has a combination of an address generating circuit and a strobe signal producing circuit for producing a plurality of strobe signals in the presence of a request signal for a burst transmission mode of operation, so that a microprocessor sequentially fetches the data words in the cache memory even if the cache memory does not cope with the nibble mode of operation.

REFERENCES:
patent: 4910656 (1990-03-01), Scales, III et al.
patent: 4912630 (1990-03-01), Cochcroft, Jr.
patent: 4912631 (1990-03-01), Lloyd

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