Cache memory controller and method for reducing CPU idle time by

Details Cache memory controller and method for reducing CPU idle time by Cache memory controller and method for reducing CPU idle time by

1991-10-18

1995-01-31

Gossage, Glenn

Boots, shoes, and leggings

395425, 364DIG1, G06F 1206, G06F 1300

Patent

active

053865260

ABSTRACT:
A cache memory controller and an associated method for fetching data are utilized to reduce the idle time of a central processing unit (CPU) of a computer system. Control circuitry and a plurality of cache fill status registers are provided to a cache controller to enable a data word to be fetched and returned to the CPU while a cache memory fill initiated due to a prior cache miss is still in progress. The data word is returned if the data word is stored in a main memory location which corresponds to a memory block offset of a main memory block frame currently being mapped into the cache memory. The data word is retrieved and returned to the CPU simultaneous with its writing into the cache memory, if the data word has not been written into the cache memory; otherwise, the data word is retrieved and returned to the CPU at the next dead cycle. As a result, CPU idle time due to cache read misses is reduced.

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"Integrated Cache Architecture Optimizes System Bus Performance", Ron Lucier; publication of the Electro 1988 Conference Record, May 10, 1988, Los Angeles, Calif., 54/3, pp. 1-6.

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