Cache memory control circuit and method for controlling reading

Details Cache memory control circuit and method for controlling reading Cache memory control circuit and method for controlling reading

1994-12-27

1996-07-09

Swann, Tod R.

395460, 395467, 395483, 395494, 395495, G06F 1200, G06F 1202, G06F 1300

Patent

active

055353584

ABSTRACT:
In cases where a remarked unit of tag addresses set in effective or access state is not registered in a tag section when a reading request is input, an external access is performed, and the remarked unit of tag addresses and other units of tag addresses respectively set in the access state are prepared in a tag entry preparing unit. In cases where a writing request is input to write a piece of updated word data in a remarked unit of data addresses corresponding to the remarked unit of tag addresses before the external access is finished, the state of the remarked tag entry prepared is changed to the effective state, and the updated word data is written in the remarked unit of data addresses of a data storing unit. Because the remarked unit of tag addresses is set in the effective state, the updated word data written in the remarked unit of data addresses is not replaced with a piece of external word data obtained according to the external access when the external access is finished. In cases where any writing request is not input until the external access is finished, the external word data is written in the remarked unit of data addresses, and the state of the remarked unit of tag addresses is changed to the effective state to replace the external word data with a piece of updated word data relating to a following writing request. Therefore, the writing and reading requests can be performed without delaying the writing request.

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