Cache memory control apparatus

Details Cache memory control apparatus Cache memory control apparatus

1986-12-15

1989-01-10

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1204

Patent

active

047978139

ABSTRACT:
A cache memory control apparatus according to the present invention includes data register blocks which are individually controlled for each byte, cache memory blocks, and a decoder for generating control signals which control the access to those blocks. In this cache memory control apparatus, when a cache hit is made in a write mode for byte data, the control signal is supplied to the data register blocks and cache memory blocks to individually control the respective blocks, thereby allowing word data corresponding to the write byte data to be synthesized. Thus, the word data can be output to an external device by one operation.

REFERENCES:
patent: 3581287 (1971-05-01), Greenspan
patent: 4298929 (1981-11-01), Capozzi
patent: 4345309 (1982-08-01), Arulpragasam et al.
patent: 4370710 (1983-01-01), Kroft
patent: 4520439 (1985-05-01), Liepa
patent: 4654781 (1987-03-01), Schwartz et al.

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