Cache memory arrangement with write buffer pipeline providing fo

Details Cache memory arrangement with write buffer pipeline providing fo Cache memory arrangement with write buffer pipeline providing fo

1993-02-02

1994-02-01

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, G06F 1314

Patent

active

052838900

ABSTRACT:
A cache memory is arranged using write buffering circuitry. This cache memory arrangement comprises a Random Access Memory (RAM) array for memory storage operated under the control of a control circuit which receives input signals representing address information, write control signals, and write cancel signals. At least one address register buffer is coupled to the address input of the RAM, while at least one data register buffer is coupled to the data input of the RAM. Thus, in accordance with the present invention, addresses to be accessed in the RAM, as well as data to be written to the RAM, are buffered prior to being coupled to the RAM. As a result, systems utilizing the cache memory arrangement of the present invention need not stall or delay the output of information toward the RAM in order to check for a cache hit or miss. Such determinations can advantageously be made while the relevant address and data are in the register buffers en route to the RAM. Any write cancels necessitated by a cache miss then abort the write prior to the coupling of the write address and data to the RAM.

REFERENCES:
patent: 4363095 (1982-12-01), Woods et al.
patent: 4442488 (1984-04-01), Hall
patent: 4527238 (1985-07-01), Ryan et al.
patent: 4875160 (1989-10-01), Brown, III
patent: 4926323 (1990-05-01), Baror et al.
patent: 4942518 (1990-07-01), Weatherford et al.
patent: 4980819 (1990-12-01), Cushing et al.

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