Cache memory architecture with decoding

Details Cache memory architecture with decoding Cache memory architecture with decoding

1980-11-17

1984-03-13

Thomas, James D.

Boots, shoes, and leggings

G06F 930, G06F 1300

Patent

active

044371497

ABSTRACT:
An information processing unit and storage system comprising at least one low speed, high capacity main memory having relatively long access time and including a plurality of data pages stored therein and at least one high speed, low capacity Cache memory means having a relatively short access time and adapted to store a predetermined plurality of subsets of the information stored in said main memory data pages. Instruction decoding means are located in the communication channel between the main Memory and the Cache which are operative to at least partially decode instructions being transferred from main Memory to Cache. The at least partial decoding comprising expanding the instruction format from that utilized in the main Memory storage to one more readily executable by the processor prior to storing said instructions in the Cache. Said decoding means includes a logic circuit means for determining whether a given instruction is susceptible of partial decoding and means for determining that a particular instruction has already been partially decoded (i.e., after a first accessing of said instruction by the processor from Cache).
In the preferred embodiment the assumption is made that the system utilizes separate Cache storage means for data and instructions respectively whereby only instructions being transferred from main Memory to Cache will pass through said decoding means.

REFERENCES:
patent: 3898624 (1975-08-01), Tobias
patent: 3928857 (1975-12-01), Carter et al.
patent: 4080648 (1978-03-01), Asano et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4371927 (1983-02-01), Wilhite et al.
patent: 4382278 (1983-05-01), Appelt

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