Cache memory architecture for microcomputer speed-up board

Details Cache memory architecture for microcomputer speed-up board Cache memory architecture for microcomputer speed-up board

1985-09-30

1988-12-27

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 928

Patent

active

047945230

ABSTRACT:
A method and apparatus for enhancing the speed of operation of a computer consists of providing a cache memory which is faster than the computer's main memory, disabling the computer's main microprocessor, and replacing it with a microprocessor with a faster clock cycle time. A portion of the program stored in the main memory is stored in the cache memory. The addresses of the portion of the main memory stored in the cache memory are noted in a tag RAM. Upon each addressing sequence during the execution of a program, the tag RAM is examined to determine if the addressed located is stored in the cache memory. If the stored location is identified in the tag RAM, it is retrieved from the cache memory at high-speed. Otherwise, the data in the address location is retrieved from main memory at a slower speed and written into the cache memory so that subsequent accesses may be made at high-speed.

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