Cache memory apparatus for reading data corresponding to input a

Details Cache memory apparatus for reading data corresponding to input a Cache memory apparatus for reading data corresponding to input a

1995-05-31

1997-05-27

Swann, Tod R.

395445, 395460, 395461, 395462, 395463, 395464, 395465, 395466, 395467, 39542103, 39542109, 395486, 395494, 39542107, 39542108, G06F 1212, G06F 1300

Patent

active

056341040

ABSTRACT:
A accordance determining circuit (113) that determines whether or not a cache address CA required in updating a cache data memory (111) and a cache tag memory (112) accords with the address of data read from an external memory (130) is provided. When the accordance determining circuit (150) has determined an accordance state, a register (115) is enabled so that cache data read from the external memory (130) is stored in a register (115) and supplied to a cache requester (101). Alternatively, a means for generating an address corresponding to the next data of data to be updated in updating the cache data memory (111) and (112) is provided so as to determine the cache status of an address being generated. Thus, if the determined result represents that the cache data has not been stored, a plurality of data are updated at a time. Consequently, the mis-hit penalty time can be reduced and the hit ratio can be improved.

REFERENCES:
patent: 5165029 (1992-11-01), Sawai et al.
patent: 5301289 (1994-04-01), Suzuki et al.
patent: 5463760 (1995-10-01), Hamauchi
English Abstract of Japanese Patent Application No. 61-5357 entitled, "Data Processor".
Harold S. Stone, "High Performance Computer Architecture", Mar. 30, 1989, Mauzen, pp. 23-42 (with translation.
Nikkei Electronics [434], Nov. 16, 1987, Nikkei BP Company, pp. 159-174.
Search Report for EP 93 90 4367.

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