Patent
1994-08-24
1998-05-19
Swann, Tod R.
395465, 395472, 395481, 395414, 395464, 39542103, 3954211, G06F 1208
Patent
active
057548145
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a cache memory apparatus for reading data at high speed for use with an information processing unit such as a microprocessor (hereinafter referred to as an MPU).
Cache memory apparatuses have been widely used to improve the processing speeds of information processing units. The technologies of the cache memory apparatuses are described in, for example:
(1) Harold S. Stone, "High Performance Computer Architecture (Translated Title)", Mar. 30, 1989, Maruzen, pp. 23-42. 159-174.
In the documents 1 and 2, the basic constructions of conventional cache memory apparatus are described. The conventional cache memory apparatus includes a memory having a smaller storage amount than an external memory so as to increase processing speeds. This memory is referred to as a cache memory. When data that is often read is stored in the cache memory, this data can be quickly read. When required data is not stored in the cache memory, it is read from an external memory of the cache memory apparatus. The required data is then read at a normal speed. Next, a practical construction of the cache memory apparatus and an operation thereof will be described.
FIG. 2 is a schematic diagram showing a basic circuit of a conventional cache memory apparatus.
In FIG. 2, reference numeral 50 is a cache memory apparatus. The cache memory apparatus 50 outputs cache data CD to a data read requester 1 (hereinafter, the data read requester is referred to as a cache requester) such as a central processing unit according to a cache address CA requested thereby.
The cache memory apparatus 50 comprises a control circuit 10, a cache tag memory 11, a cache data memory 12, and an accordance determining circuit 13. The control circuit 10 controls inner circuits of the cache memory apparatus 50. The cache tag memory 11 is constructed of a small-capacity, high-speed random access memory (hereinafter referred to as RAM) or the like. The cache data memory 12 is also constructed of a RAM or the like. The cache tag memory 11 stores part of addresses of data stored in the cache data memory 12. The cache tag memory 11 has an address terminal A, a data input/output terminal D (hereinafter referred to as an I/O terminal), a write enable terminal WE, and terminals VAi and VAo. The write enable terminal WE is activated by the control circuit 10. Likewise, the terminals VAi and VAo are activated by the control circuit 10. The cache data memory 12 stores data that is often read. The cache data memory 12 has an address terminal A, an I/O terminal D, and a write enable terminal WE. The write enable terminal WE is activated by the control circuit 10. The accordance determining circuit 13 has an enable terminal E. When the enable terminal E is activated, the accordance determining circuit 13 detects whether or not two information accord with each other. When the two information accord with each other, the accordance determining circuit 13 outputs a hit signal HIT.
The cache memory apparatus 50 also comprises registers 14 and 15, an external register 16, tri-state buffers 17, 18, 20, and 21, an AND gate 19, and an IA bus 22. The register 14 has an enable terminal E. When the enable terminal E is activated with a hit signal HIT, the register 14 stores a cache address CA. The register 15 also has enable terminal E. When the enable terminal E is activated with a hit signal HIT, the register 15 stores cache data CD that is received through an ID bus 23. The external register 16 has a count enable terminal CE. When the count enable terminal CE is activated by the control circuit 10, the external register 16 stores an address EA. The tri-state buffers 17, 18, 20, and 21 are controlled by the control circuit 10.
Address terminals A of the cache tag memory 11 and the cache data memory 12 are connected to the output side of the register 14, which stores a cache address CA, through the tri-state buffer 17 and the IA bus 22. The register 14 outputs the number of bits a of a cache address CA to the IA bus 22. Log.sub.2 (the
REFERENCES:
patent: 4970643 (1990-11-01), Cramm
patent: 5123108 (1992-06-01), Olson et al.
patent: 5485589 (1996-01-01), Kocis et al.
Harold S. Stone, "High Performance Computer Architecture", mar. 30, 1989, Mauzen, pp. 23-42 with translation.
Manzo Edward D.
Murphy Mark J.
OKI Electric Industry Co., Ltd.
Swann Tod R.
Tran D.
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