Cache memory and data processor including instruction length dec

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395450, 395375, 364DIG1, G06F 1204, G06F 1300, G06F 930

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054887100

ABSTRACT:
A cache memory, and a data processor including the cache memory, for processing at least one variable length instruction from a memory and outputting processed information to a control unit, such as a central processing unit (CPU). The cache memory includes a unit for decoding an instruction length of a variable length instruction from the memory, and a unit for storing the variable length instruction from the memory, together with the decoded instruction length information. The variable length instruction and the instruction length information thereof are fed to the control unit. Accordingly, the cache memory enables the control unit to simultaneously decode a plurality of variable length instructions and thus realize high speed processing.

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Tron Specification Chip-Architecture Overview, by Ken Sakamura Ver.1.00.00.00, 1991, pp. 1-10, 86-91 and title page.

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