Cache memory addressable by both physical and virtual addresses

Details Cache memory addressable by both physical and virtual addresses Cache memory addressable by both physical and virtual addresses

1989-06-16

1991-02-05

Anderson, Lawrence E.

Boots, shoes, and leggings

36424341, 3642563, G06F 1208

Patent

active

049910817

ABSTRACT:
A cache memory addressable by both physical and virtual addresses includes a cach data memory (64) and a tag memory (66). The tag memory (66) is comprised of a virtual tag memory (68) and a physical tag memory (70). The physical and virtual tag memories are both addressable by the least significant bits (LSB) of the address signal to output tag portions of addresses associated with data stored in the cache data memory (64). A switch (78) selects between the outputs from the memories (68) and (70) under control of an arbitration unit (88). The arbitration unit (88) distinguishes between virtual or physical addresses input thereto. A comparator (100) compares the selected tag portion with the tag portion of the received address to determine if a match exists. If a match exists, the output of the cache data memory is selected with a switch (84).

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