Cache lock information feeding system using an address translato

Details Cache lock information feeding system using an address translato Cache lock information feeding system using an address translato

1994-11-10

1996-01-23

Kim, Matthew M.

Boots, shoes, and leggings

364DIG1, 36424341, 395403, 395413, G06F 1208

Patent

active

054871620

ABSTRACT:
A method and apparatus for cache lock control are designed for use with a cache memory. The cache memory contains a number of data entries, each divided into segments for storing address information, data, and a cache lock bit, respectively. The cache lock bit, when set in a data entry, prevents updating the address and data in that data entry. An address translator is provided for converting virtual memory addresses to physical addresses. The address translator includes address entries which include at least one segment for storing cache lock information, and cache lock information is transferred from the address translator to the cache memory.

REFERENCES:
patent: 4638426 (1987-01-01), Chang et al.
patent: 5029072 (1991-07-01), Moyer et al.
patent: 5163143 (1992-11-01), Culley et al.
patent: 5168568 (1992-12-01), Thayer et al.
patent: 5249286 (1993-09-01), Alpert et al.
patent: 5297270 (1994-03-01), Olson
"Sparc Risc User's Guide" by Cypress Semiconductor, Feb. 1990, pp. 4-18 to 4-19 and 4-34 to 4-35.

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