Cache line replacement with zero latency

Details Cache line replacement with zero latency Cache line replacement with zero latency

2005-10-18

2009-11-17

Nguyen, Steven (Department: 2416)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C711S113000, C711S143000

Reexamination Certificate

active

07620057

ABSTRACT:
A method for cache management includes assigning a respective cache line in a cache of a processing device to each of a plurality of processing flows in the processing device, and loading respective context data relating to each of the processing flows from a memory into the respective cache line that is assigned thereto. Respective activity levels of the processing flows are monitored. Responsively to detecting an absence of activity of a processing flow, and prior to receiving a request to overwrite the cache line, the context data are written back to the memory from the respective cache line that is assigned to the processing flow.

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