Cache line branch prediction scheme that shares among sets of a

Details Cache line branch prediction scheme that shares among sets of a Cache line branch prediction scheme that shares among sets of a

1996-09-19

1998-06-30

Treat, William M.

395587, 39580023, 39580041, G06F 938

Patent

active

057747105

ABSTRACT:
A microprocessor includes an instruction cache and a branch target buffer to implement a branch prediction scheme. The instruction cache, which stores branch instructions, is organized into cache lines and sets to implement set associative caching with memory that stores instructions. The branch target buffer includes storage locations organized into lines such that instructions stored in a cache line of the instruction cache correspond to a line in the branch target buffer. The storage locations permit storage of a branch target address that corresponds to any one of the sets in the cache line of the instruction cache to permit storage of branch information for multiple branch instructions when a cache line of a set stores more than one branch instruction. Thus, the resources of the branch target buffer are shared among the sets of the instruction cache.

REFERENCES:
patent: 5265213 (1993-11-01), Weiser et al.
patent: 5367703 (1994-11-01), Levitan
patent: 5663965 (1997-09-01), Seymour

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